Design And Verification Conference & Exhibition India 2025

DVCon India typically offers a rich technical program. Based on past editions and the industry’s direction, here are likely themes:

• Advanced Verification Methodologies:
  • UVM (Universal Verification Methodology): Advanced techniques, UVM adoption challenges and solutions, UVM for analog/mixed-signal (AMS).
  • Portable Stimulus Standard (PSS): Its application for generating tests across different verification levels (IP, subsystem, SoC, emulation, post-silicon).
  • Formal Verification: Leveraging formal methods for exhaustive verification and bug hunting.
  • Hardware Acceleration and Emulation: Using these powerful platforms for faster verification of complex SoCs.
  • AI/ML in Verification: Emerging trends in applying Artificial Intelligence and Machine Learning for verification efficiency, bug prediction, and test generation.
• System-Level Design and Verification (ESL Track):
  • SystemC and Virtual Prototypes: Early software development, architectural exploration, performance, and power analysis using virtual models.
  • High-Level Synthesis (HLS): Design creation from high-level models.
• Functional Safety and Security:
  • Verification challenges for safety-critical applications (e.g., automotive, aerospace).
  • Techniques for ensuring security in hardware designs.
• Low-Power Design and Verification: Methodologies using standards like UPF for power-efficient chip design.
• Analog/Mixed-Signal (AMS) Verification: Specific challenges and solutions for designs integrating analog and digital components.
• IP Reuse and Design Automation: Best practices for integrating and verifying third-party Intellectual Property (IP) and automating design flows.
• Design Automation Tools and Flows: Latest advancements in EDA tools and their effective integration into design flows.
• Post-Silicon Validation: Bridging the gap between pre-silicon verification and post-silicon bring-up and debugging. What to Expect for Attendees: A Comprehensive Experience

• Keynote and Invited Talks: Insights from industry veterans, thought leaders, and policymakers on the future of design and verification.
• Technical Paper Presentations: In-depth sessions showcasing cutting-edge research, innovative solutions, and practical case studies. The conference typically runs with two parallel tracks (ESL and D&V).
• Tutorials: Hands-on learning opportunities and deep dives into specific tools, methodologies, or standards, often led by experts.
• Panel Discussions: Lively debates and discussions on trending topics and industry challenges, featuring diverse perspectives.
• Poster Sessions: Opportunities to interact directly with authors and discuss their research in a more informal setting.
• Exhibition: A dedicated area featuring booths from leading EDA tool vendors, IP providers, and service companies, showcasing their latest offerings and providing demonstrations.
• Networking Reception: A crucial event for connecting with peers, experts, and potential collaborators from across the industry.
• Submission Deadlines: While the specific Call for Papers (CFP) for DVCon India 2025 might have deadlines passed or be upcoming, generally, abstract submissions happen earlier in the year (e.g., around April-May), with final paper submissions in July. (For VDAT 2025, which is related to VLSI design and verification, the paper submission deadline was extended to May 15, 2025). It’s crucial to check the official DVCon India website for 2025’s exact dates.
• Topics of Interest: Encourage submissions related to the core themes mentioned above, including novel approaches, case studies, and contributions to industry standards.
• Submission Guidelines: Briefly mention requirements like original, unpublished work, adherence to specific formats (e.g., IEEE two-column), and a blind review process.
• Exhibitor Opportunities: For companies, emphasize the chance to showcase products, connect with a targeted audience, and generate leads.